With the design trend in electronic devices is toward lighter, smaller, thinner but more functional devices with performance requirements continuing to increase, device manufacturers increasingly need specialty integrated circuit (IC) solutions for allowing billions of miniature electronic components to be densely packed in a small area. Thus, device manufacturers come up with innovative packaging techniques for embedding electronic components in a substrate while allowing shorter traces between the electronic components and the substrate. In addition, the layout area is increased by the use of built-up technique as the technology advances for achieving lighter, smaller, thinner and more functional high-performance devices.
Generally, most high-end chips are packaged by flip chip (FC) process, especially by a chip scale package (CSP) process, as those high-end chips are primarily being applied in smart phones, tablet computers, network communication devices, and notebook computers, whichever is generally operating under high-frequency and high-speed condition and required to be packed in a thin, small and light-weighted semiconductor package. As for the carrier for packaging, the popular design nowadays includes: small pitches between lines, high density, thin-type design, low manufacture cost, and high electrical characteristic.
Generally, by the application of coreless substrate technology, the limitation of those conventional substrates for having to have a rigid bismaleimide trizaone (BT) core layer or a FR-5 core layer can be relieved and thus not only the material cost in the substrate fabrication can be reduced as the amount of layers to be formed in a substrate is decreased, but also the I/O density in a substrate is increased. It is noted that the conventional coreless substrate includes primarily the molded interconnection substrate (MIS) and the embedded pattern plating (EPP) substrate.
Please refer to FIG. 1, which is schematic diagram showing a conventional molding compound coreless substrate structure with MIS. As shown in FIG. 1, the molding compound substrate structure 10 comprises: a first conductive pillar layer 100, a metal layer 110, a second conductive pillar layer 120, a molding compound layer 130, a dielectric material layer 140, a third conductive pillar layer 150 and a solder resist layer 160. Wherein, the first conductive layer 100 is formed with a top surface and a bottom surface that are arranged opposite to each other, while allowing the metal layer 110 to be disposed on the bottom surface and the second conductive pillar layer 120 to be disposed on the top surface; the molding compound layer 130 is disposed within a specific portion of the first conductive pillar layer 100 and the second conductive pillar layer 120; the dielectric material layer 140 is disposed on the molding compound layer 130; the third conductive pillar layer 150 is disposed on the second conductive pillar layer 230, the molding compound layer 130 and the dielectric material layer 140; and the solder resist layer 160 is disposed on the dielectric material layer 140 and the second conductive pillar layer 150.
Nevertheless, the aforesaid conventional molding compound substrate structure still has shortcomings, as following: (1) It is required to have a process for forming an additional dielectric material layer 140 for solving the insufficient binding force issue between the molding compound layer 130 and the other conductive pillar layers so as to fabricate fine-line products. Nevertheless, the additional process for forming the dielectric material layer 140 not only is going to increase the steps to be performed in the fabrication process, but also is going to increase the production cost. (2) As the solder resist layer 160 is designed to be disposed between the dielectric material layer 140 and the third conductive pillar layer 150, in a ball grid array (BGA) packaging process, the reliability of any posterior process can be adversely affected by the resolution of solder mask opens in the BGA and the film thickness uniformity of the solder resist layer 160 as well.
Please refer to FIG. 2, which is schematic diagram showing a conventional embedded pattern plating (EPP) coreless substrate structure. As shown in FIG. 1, the EPP substrate structure 20 comprises: a first conductive pillar layer 200, a second conductive pillar layer 210, a dielectric material layer 220, a third conductive pillar layer 230, a first solder resist layer 240, a second solder resist layer 250, a first electrode layer 260 and a second electrode layer 270. Wherein, the first conductive layer 200 is formed with a top surface and a bottom surface that are arranged opposite to each other, while allowing the second conductive pillar layer 210 to be disposed on the top surface, and the dielectric material layer 220 to be disposed within a specific portion of the first conductive pillar layer 200 and the second conductive pillar layer 210; the third conductive pillar layer 230 is disposed on the second conductive pillar layer 210 and the dielectric material layer 220; the first solder resist layer 240 is disposed on the first conductive pillar layer 200 and the dielectric material layer 220; the second solder resist layer 250 is disposed on the third conductive pillar layer 230 and the dielectric material layer 220; the first electrode layer 260 is disposed on the bottom surface of the first conductive pillar layer 200; and the second electrode layer 270 is disposed on the third conductive pillar layer 230.
Similarly, the aforesaid EPP substrate structure 20 still has the following shortcomings, that is, as the first solder resist layer 240 is designed to be disposed on the first conductive pillar layer 200 and the dielectric material layer 220, while the second solder resist layer 250 is disposed on the third conductive pillar layer 230 and the dielectric material layer 220, in a ball grid array (BGA) packaging process, the reliability of any posterior process can be adversely affected by the resolution of solder mask opens in the BGA and the film thickness uniformity of the two solder resist layers 240, 250 as well.